1 ssc5000series dot matrix lcd controller driver pf775-03 n description the SED1230 series is a dot matrix lcd controller driver for character display, and can display a maximum of 48 characters, 4 user-defined characters, and a maximum of 64 symbols by means of 4-bit, 8-bit or serial data sent from a microcomputer. a built-in character generator rom is prepared for 256 character types, and each character font consists of 5 7 dots. a user-defined character ram for four characters of 5 7 dots are incorporated, and a symbol register is also incorporated. with these, it is possible to apply this series to display with a high degree of freedom. this series can operate handy units with a minimum power consumption by means of its low power consumption and standby mode. the SED1230 series are classified into SED1230, sed1231, sed1232, and sed1233 depending on the duty of use and the number of display columns. n features l built-in display ram 48 characters + 4 user-defined characters + 64 symbols l cgrom (for up to 256 characters), cgram (4 characters), and symbol register (64 symbols) l number of display columns number of lines (12 columns + 1 column for signal) 4 lines + 52 symbols: SED1230 (12 columns + 1 column for signal) 3 lines + 52 symbols: sed1231 (12 columns + 1 column for signal) 2 lines + 52 symbols: sed1232 16 columns 2 lines + 64 symbols: sed1233 l cr oscillating circuit (incorporating c and r) l high-speed mpu interface interfacing with both 68 series and 80 series mpu interfacing in 4 bits/8 bits l serial interface l character font 5 7 dots l duty ratio 1/16 (sed1232, sed1233) 1/23 (sed1231) 1/30 (SED1230) l simple command setting l built-in liquid crystal driving power circuit voltage boosting circuit, voltage regulating circuit, voltage follower 4 l built-in electronic volume function l low power consumption 100 m a max. (in normal operation mode: including the operating current of the built-in power supply) 20 m a max. (in standby display mode) l power supply v dd - v ss (logic section): C2.4 v to C3.6 v v dd - v 5 (liquid crystal drive section): C5.0 v to C11.0 v (in the case of external power supply) l wide operating temperature range ta = -30 to 85 c l cmos process l package: die form sed123 * d * b , sed123 * d * e (au bump) sed123 * d * a , sed123 * d * c (al pad) tcp sed123 * t ** l this ic is not designed with a protection against radioactive rays. l 12 character 4 line (5 7 dot) l built-in character generator rom and ram l built-in power supply circuit for lcd SED1230 series
2 SED1230 series n block diagram d6 (scl) input buffer mpu interface address counter command decoder cursor control seg driving circuit com driving circuit refresh address counter ram cgrom timing generating circuit oscillator power circuit d0 d1 d2 d3 d4 d5 d7 (si) if res cs wr (e) p/s a0 seg1?0 seg1? com1?8 coms1? v 1 v 2 v 3 v 4 v 5 cap1+ cap1 cap2+ cap2 v r v out v s1
3 SED1230 series n pad specification SED1230d ** 1/30 duty 12 columns + 1 signal column sed1231d ** 1/23 duty 12 columns + 1 signal column sed1232d ** 1/16 duty 12 columns + 1 signal column sed1233d ** 1/16 duty 16 columns #1 column for cgrom pattern change chip size: 10.23 3.11 mm pad pitch: 110 m m (min.) chip thickness: 625 25 m m (sed123 * d * a , sed123 * d * b ) 525 25 m m (sed123 * d * c , sed123 * d * e ) 1) a1 pad specification (sed123 * d * a ) pad size: a 86 m m 135 m m b 135 m m 86 m m 2) au bump specification (sed123 * d * b * ) for reference: bump sizea 80 m m 129 m m b 129 m m 80 m m bump height 22.5 m m 5.5 m m n absolute maximum ratings notes: 1. all the voltage values are based on v dd = 0 v. 2. for voltages of v 1 , v 2 , v 3 and v 4 , keep the condition of v dd 3 v 1 3 v 2 3 v 3 3 v 4 3 v 5 at all times. 3. if the lsi is used exceeding the absolute maximum ratings, it may lead to permanent destruction. in ordinary operation, it is desirable to use the lsi in the condition of electrical characteristics. if the lsi is used out of this condition, it may cause a malfunction of the lsi and have a bad effect on the reliability of the lsi. rating symbol value unit power supply voltage (1) v ss C6.0 to +0.3 v power supply voltage (2) v 5 C16.0 to +0.3 v power supply voltage (3) v 1 , v 2 , v 3 , v 4 v 5 to +0.3 v input voltage v in v ss C0.3 to +0.3 v output voltage v o v ss C0.3 to +0.3 v operating temperature t opr C30 to +85 c storage temperature tcp t str C55 to +100 c bare chip C75 to +125 (v cc ) v dd (gnd) v ss v dd v 5 (0,0) 173 174 193 1 58 69 85 86 -
4 SED1230 series n dc characteristics (v dd = 0 v, v ss = C3.6 v to C2.4 v, ta = C30 to 85 c unless otherwise specified.) characteristic symbol condition min. typ. max. unit applicable pin power recommended C3.6 C3.0 C2.4 v v ss supply operation v ss voltage (1) operable C5.5 C3.0 C2.0 *1 power recommended C11.0 C5.0 v v 5 supply operation v 5 voltage (2) operable C11.0 C4.5 *2 operable v 1 , v 2 0.6 5 v 5 v dd vv 1 , v 2 operable v 3 , v 4 v dd 0.8 5 v 5 vv 3 , v 4 high-level input voltage v ihc 0.2 5 v ss v dd v*3 low-level input voltage v ilc v ss 0.8 5 v ss v*3 input leakage current i li v in = v dd or v ss C1.0 1.0 m a*3 lc driver on resistance r on ta=25 cv 5 =C7.0v 20 40 k w com,seg d v=0.1v *4 static current consumption i ddq 0.1 5.0 m av dd dynamic current i dd display state v 5 = C7 v without load 100 m av dd *5 consumption standby state oscillation on, 20 m av dd *6 power off sleep state oscillation off, 5 m av dd power off access state f cyc =200khz 500 m av dd *7 input pin capacity c in ta=25 c f=1mhz 5.0 8.0 pf *3 reset time t r 1.0 m s*8 reset pulse width t rw 10 m s*9 input voltage v ss C3.6 C2.4 v *10 booster output voltage v out double boosting state C7.2 v v out triple boosting state C10.8 voltage follower v 5 C11.0 C4.5 v operating voltage reference voltage v reg ta = 25 c C3.5 C3.1 C2.7 v *1: a wide operating voltage range is guaranteed but an abrupt voltage variation in the access status of the mpu is not guaranteed. *2: the operating voltage range is applicable to the case where an external power supply is used. *3: d0 - d5, d6 (scl), d7 (si), a0, res, cs, wr (e), p/s, if *4: this is a resistance value when a voltage of 0.1 v is applied between output pin segn, segsn, comn or comsn, and each power pin (v 1 , v 2 , v 3 or v 4 ). it is specified in the range of operating voltage (2). ron = 0.1 v / d i ( d i: current flowing when 0.1 v is applied between the power and output) *5: character display. this is applicable to the case where no access is made from the mpu and the built-in power circuit and oscillating circuit are in operation. *6: this is applicable to the case where the built-in power circuit is off and the oscillating circuit is in operation in the st andby mode. *7: current consumption when data is always written by fcyc. the current consumption in the access state is almost proportional to the access frequency (fcyc). when no access is made, only idd (i) occurs. *8: t r (reset time) indicates the internal circuit reset completion time from the edge of the res signal. accordingly, the sed123 * usually enters the operating state after t r . *9: the minimum pulse width of the res signal is specified. to cause a reset operation, it is necessary to input a pulse width exceeding t rw . *10: when operating the boosting circuit, the power supply v ss must be used within the input voltage range. built-in power supply
5 SED1230 series n charactor font (jis type standard) l sed123 * d a * h i g h e r 4 b i t o f c o d e 6 7 8 9 01234 5678 9abcdef 0 1 2 3 4 5 a b c d e f lower 4 bit of code
6 SED1230 series l sed123 * d b * 9 6 7 8 a b c d e f 01234 5678 9abcdef 0 1 2 3 4 5 h i g h e r 4 b i t o f c o d e lower 4 bit of code
7 SED1230 series l sed123 * d g * 9 6 7 8 a b c d e f 01234 5678 9abcdef 0 1 2 3 4 5 lower 4bit of code h i g h e r 4 b i t o f c o d e
8 SED1230 series electronic devices marketing division electronic device marketing department ic marketing & engineering group 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5816 fax: +81-(0)42-587-5624 ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5812 fax: +81-(0)42-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-(0)42-587-5814 fax: +81-(0)42-587-5110 notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liabilit y of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circu it and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, med ical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic pr oducts under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. all product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ?seiko epson corporation 1998 all rights reserved. http://www.epson.co.jp electric device information of epson www server
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